cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 1/9 mta012a02cdn6 cystek product specification common drain dual n -channel enhancement mode mosfet mta012a02cdn6 features ? simple drive requirement ? low gate charge ? low on-resistance ? fast switching speed ? esd protected gate ? pb-free lead plating and halogen-free package equivalent circuit outline ordering information device package shipping MTA012A02CDN6-0-T1-G sot-26 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel mta012a02cdn6 g gate s source d drain environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel, 7? reel product rank, zero for no rank products product name sot-26 pin #1 bv dss 20v i d v gs =4.5v, t a =25 c 7a v gs =4.5v, i d =5a 15.3 m v gs =2.5v, i d =2.6a 18.5 m r dson ( typ .) v gs =1.8v, i d =1a 30.5 m
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 2/9 mta012a02cdn6 cystek product specification absolute maximum ratings (ta=25 c, unless otherwise specified) parameter symbol limits unit drain-source voltage v ds 20 gate-source voltage v gs 8 v continuous drain current @ v gs =4.5v, t c =25 c 12.4 continuous drain current @ v gs =4.5v, t c =100 c 7.8 continuous drain current @ v gs =4.5v, t a =25 c 7 continuous drain current @ v gs =4.5v, t a =70 c i d 5.6 pulsed drain current i dm 50 *1, 2 a t a =25 2 *3 total power dissipation t a =70 p d 1.3 *3 w operating junction and storage temperature range tj, tstg -55~+150 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 20 thermal resistance, junction-to-ambient, max r ja 62.5 *3 c/w note : 1. pulse width limited by maximum junction temperature. 2. duty cycle 1%. 3. surface mounted on a 1 in2 pad of 2oz copper. in practice r th,j-a will be determined by the customer?s pcb characteristics. electrical characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 20 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 0.02 - v/ c reference to 25 c, i d =250 a v gs(th) 0.4 - 1.0 v v ds =v gs , i d =250 a i gss - - 20 v gs =8v, v ds =0v - - 1 v ds =20v, v gs =0v i dss - - 10 a v ds =16v, v gs =0v, tj=70 c - 15.3 22 i d =5a, v gs =4.5v - 18.5 30 i d =2.6a, v gs =2.5v *r ds(on) - 30.5 65 m i d =1a, v gs =1.8v *g fs - 4.8 - s v ds =10v, i d =1a dynamic ciss - 680 - coss - 186 - crss - 31 - pf v ds =10v, v gs =0v, f=1mhz
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 3/9 mta012a02cdn6 cystek product specification *t d(on) - 82.4 - *t r - 46.8 - *t d(off) - 319.4 - *t f - 888.8 - ns v ds =10v, i d =5a, v gs =4.5v, r g =6 ? *qg - 10.5 - *qgs - 1 - *qgd - 3.1 - nc v ds =16v, i d =5a, v gs =4.5v source-drain diode *i s - - 3 *i sm - - 5 a *v sd - 0.76 1.2 v i s =1.2a,v gs =0v *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 4/9 mta012a02cdn6 cystek product specification typical characteristics typical output characteristics 0 10 20 30 40 012345 vds, drain-source voltage(v) i d , drain current (a) 8v, 7 v,6v,5v,4v,3v,2.5v v gs =2v v gs =1.5v brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) 1.8v 2.5v 4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 048121620 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 012345678 v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =5a drain-source on-state resistance vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =4.5v, i d =5a r dson @ tj=25c : 15.3 m typ
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 5/9 mta012a02cdn6 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0 5 10 15 20 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =10v gate charge characteristics 0 1 2 3 4 5 02468101214 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =16v i d =5a maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =4.5v, r ja =62.5c/w single pulse dc 100ms r dson limited 100 s 1ms 1s 10ms maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 8 9 10 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =4.5v, r ja =62.5c/w
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 6/9 mta012a02cdn6 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 5 10 15 20 25 30 35 40 012345 v gs , gate-source voltage(v) i d , drain current(a) v ds =5v single pulse power rating, junction to ambient (note on page 2) 0 50 100 150 200 250 300 350 400 450 500 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width(s) power (w) t j(max) =150c t a =25c r ja =62.5c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =62.5c/w
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 7/9 mta012a02cdn6 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 8/9 mta012a02cdn6 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c779n6 issued date : 2018.04.11 revised date : page no. : 9/9 mta012a02cdn6 cystek product specification sot-26 dimension millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 1.050 1.250 0.041 0.049 e 1.500 1.700 0.059 0.067 a1 0.000 0.100 0.000 0.004 e1 2.650 2.950 0.104 0.116 a2 1.050 1.150 0.041 0.045 e 0.950 (bsc) 0.037 (bsc) b 0.300 0.500 0.012 0.020 e1 1.800 2.000 0.071 0.079 c 0.100 0.200 0.004 0.008 l 0.300 0.600 0.012 0.024 d 2.820 3.020 0.111 0.119 0 8 0 8 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . marking: 6-lead sot-26 plastic surface mounted package cystek package code: n6 style: pin 1. source 1 (s1) pin 2. drain1/drain2 (d1/d2) pin 3. source 2 (s2) pin 4. gate 1 (g1) pin 5. drain 1/drain 2 (d1/d2) pin 6. gate 2 ( g2 ) 12a02 device name date code 6 5 4 1 2 3
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